Whoa, a full course on this out issue. Thank you so very much for taking the time to go through it like that. I will dig in, in the morning, with some fresh coffee in my veins.
The time aspect is all new, I am excited to get some understanding of it.
Time, it is the time aspect. After reading through your posts, I think I see what I was mistakenly assuming. The circuit works, I have the basics but never even considered the speed at which it all happens, just never had to. Just being over Vth makes it work slower, I understand it just never even considered it.
I never thought the .000000001seconds would matter.
And if I am being honest, I am just now starting to see pull-ups and pull-downs as a normal thing. I always just thought âhow the hell is that not causing a short and burning up"? As an ME we learned all this stuff in terms of plumbing, and this is where that analogy breaks down. A resistor being a constricted hose makes no sense for a pull down.
So many times I have wanted to start taking a Briliant.com EE course or something so I can learn it right.
Okay, I was doing that wrong. I got the divider part right, but I thought it was source-gate=Vgs. So I would do 24V-19.3V and get a Vgs of 4.7v (low but fine) or 5V-3.34=1.66v (well into the trouble zone of the curve). Okay, now I know to do it the way you showed.
Where I am stuck, exactly right here. Using your correct math (or even my incorrect math, same logic problem for me), why the heck does this not work at the 24V setting? -19.3V (or -4.7)Vgs seems well above the curve (Vth), and should not be slow. I thought I understood why the 5V side doesnât work well, but if I was right the 24v side SHOULD work but it does not.
I understand this
Had my hopes up there for a second, as that looks simple to use.
I have the 5V buffer in now, but I am reading that as 24v pwm is out of the question. Unless I do two separate circuits with separate outputsâŚ..or use the same outputs with jumpers or something to select them.
Right. My apologies, I had forgotten that you might still be trying to speed up the high-side switch state. A week of being out of town for work kinda factory reset me a little. That makes my 2 hour rant a little less relevant.
Unfortunately timing stuff gets complicated quickly. Not impossible, just harder. The kinda âshort storyâ there is that if you want things to be fast, itâs better to have driven logic where both the rising and falling edges are caused by FETs switching, not just driven in one direction and then allowed to be pulled/float down in the other direction. Itâs not impossible for the latter to be fast, indeed thatâs how I2C works, but itâs a lot more difficult and requires significant design time to verify it all.
Given that weâre already switching between 5V and Vmot, is there any specific situation where we would absolutely need PWM at Vmot or 2A drive at 5V? Powering something significant from 5V should probably be done by an external step-down converter at 24V anyway. Most things that can accept a PWM signal should be fine at 5V?
Yeah, kinda. Basically the FET is a voltage controlled resistor. As you apply voltage to the gate it creates an electric field across a piece of semiconductor that creates a conductive path, essentially squeezing it shut or opening it up, depending on the type of FET. Again to use the water analogy itâs like a ball valve thatâs servo controlled. No voltage applied, no opening. A little bit of voltage applied, say 2V, you get the first drips. Beyond that, the valve just opens more. Even at 8V or 10V, the valve isnât fully open, but itâs open enough that going from 2V to 4V makes a huge difference, 4V to 6V less so, etc.
All of this isnât really anything to do with âspeedâ, as such. If all youâre trying to do is catch a drip and we donât care what happens afterwards, giving it 2V will be as fast as 10V. Thatâs basically capacitance. Trying to fill a thimble would be small capacitance, trying to fill a barrel would be a big electrolytic capacitor. The issue is that big FETs (big valves) have big output capacitances (I guess the analogy would be large pipes) to âfillâ. The other aspect is that the gate itself is a capacitor that needs to be filled, so youâre controlling your ball valve by filling up a bucket of water. Big, high current FETs have big buckets to fill to control how much theyâre on. Small, low current FETs have small buckets and can be filled quickly.
As an interesting aside, when weâre dealing with switch-mode power supplies, we want that FET to switch as fast as possible usually, because while itâs half on you have high current and high voltage across the FET, which means lots of loss. You can never switch instantly, but we try to minimize it. âFastâ at 1200V/100A would be in the 20-40ns range. Thatâs switching a very big FET with very large capacitances very quickly. To do that, we need to put a lot of current into the gate. We do that with dedicated ICs that do nothing but take the logic input and turn it into a very high current output specifically designed to quickly fill/empty those capacitors. Our âstandardâ sized gate drive was about 9A peak output current at +18V/-5V, so basically +24V of voltage change at 9A peaks. Overall only around 1-2W per FET, but we would have 8-10W of circuitry thatâs there just turning the FETs on and off. Thatâs pretty close to the same power used to drive the motion stage in an LR4!
It creeps up on you quickly. 10kHz is pretty slow, 100us periods isnât too bad. Then once you add PWM to that, it quickly becomes that you donât really want 10kHz, you want 10kHz at say 14% duty cycle. Which means youâre now talking about a 14us pulse every 100us. If you want that 14us pulse to be accurate, you really need your rise and fall times to be ~10% of the minimum width to have it still look like a square wave and not have a huge offset. Thatâs suddenly 1.4us rise and fall times. Still pretty slow relative to most logic, but enough to be irritating in this scenario.
100% understood, and I think this is where doing this ad-hoc and via forum posts is making it a little difficult. These are all basic techniques that would be quick to cover in a learning environment or as explaining things, but the friction behind asking questions about that and writing the answers out is enough to slow it down.
Basically, though, pretty much everything should have some form of series resistance to limit peak currents and everything should have some form of pull-up/pull-down to control states during high-Z periods.
Dealing with plumbing analogies definitely gets limiting, but not impossibly so. Youâve just gotta keep in mind that theyâre a limited and imperfect means to understand one single concept at a time, not a cohesive set of rules that maps perfectly. A FET is a ball valve with a bucket hanging off the handle and a spring pulling it closed. Fill the bucket with water (charge the gate capacitance), the valve opens more (the conductive channel forms/widens). Empty the bucket (discharge the gate capacitance) and the valve closes more (the channel shrinks/pinches). The more open the valve (the more open the channel, the lower the channel resistance), the more water flow/less pressure drop (less voltage drop for a given current, more current at the same input voltage) etc. Trying to map anything onto that further gets difficult. The valve has no inertia and no resistance to being turned. The valve overheats if itâs partially open and thereâs lots of flow through it. That heating is the main way we choose valves and you can have 2 valves that have the same size orifice when fully open but that can handle different flow rates for different periods of time. All of that you can kinda hand-wave your way into, but it just gets less and less useful compared to just explaining the underlying physics. The thing controlling the flow of electrons isnât physical, itâs an electric field and charge carriers in a semiconductor. The specifications of the FET isnât solely defined by the silicon die itself, but also the package itâs in, the leads that are connected to it and the cooling solution used. Different methods of physically making the FET in terms of how itâs layered up in 2D/3D space and how things are connected together internally can mean that 2 devices with the same voltage/current/resistance in the datasheet may perform very differently in terms of speed, how they switch, what it takes to drive them, etc.
Go for it. It doesnât have to be a ton of time, but the 2nd best time to start is now. Even doing a little bit at a time is good because it can shake questions loose that we can answer here or that may clarify something youâve already learned in a way that connects it back to something else etc.
Yeah, P-channel FETs are kinda awful like that. Theyâre actually somewhat uncommon to use these days as discrete parts, theyâre in almost every piece of silicon ever but normally in an integrated circuit so youâre not dealing with them directly. If you look carefully at the symbol, youâll see theyâre often drawn into a circuit upside down because thatâs what allows us to stick with the convention that current flows from top to bottom and left to right. No reason for that other than convention, of course, and in reality positive current is negatively charged electrons flowing backwards etc. but itâs best not to stare into that particular void for too long!
So thatâs a âright way upâ drawing of an N-channel and P-channel enhancement mode MOSFET. If they show the body diode then thatâs the easy way to identify them in that itâs backwards compared to the other type, but the actual definitive thing is the arrow. You may not be aware of this, but the diagram of the FET actually represents the way the semiconductor itself is physically constructed, at least in a somewhat abstract way. There is a âstripâ of semiconductor that gets âdopedâ (essentially that just means forcing impurities into the pure silicon so it has either excess electrons or excess spaces for electrons to be) such that it almost conducts but doesnât quite have enough charge carriers. On either side of that strip are insulated conductors that forms the plates of a capacitor with the strip in the middle. As the capacitor is charged up, an electric field is created that causes charge carriers to get pulled into the strip such that it starts to become conductive. More voltage on the capacitor plates means stronger electric field which means more charge carriers come in which means lower resistance.
The G and Sub connections are to 2 black lines that represent the plates of the capacitor. Sub just means âsubstrateâ, because thatâs how itâs made, usually thatâs just the bottom of the stack and where things get stuck down via. The D and S connections are at either end of the semiconductive strip. Looking at the symbol for the MOSFET again, you can see how the lines match up to their respective physical counterparts. The big unbroken line connected to the gate represents one side of the capacitor. The 3 shorter lines opposite it are the 3 other connections to the semiconductor. The arrow on the other side of the gate isnât a diode, itâs telling you how the semiconductor was made and therefore what polarity of voltage needs to be applied to make it change resistance.
The N and P sections denote different types of semiconductor doping, N meaning it has extra electrons floating around unneeded, P meaning it has a lot of missing spots where electrons should be. If it were just a N or P section, it would conduct because electrons flowing in could make it through to the other side. If it were just an N and a P, thatâs a diode where it will conduct from P to N (electrons fill the holes in the P section and push through until they knock out the extras in the N section) but wonât from N to P (electrons get bunched on the N section with nowhere to go, more complicated than that but thatâs the gist). With the NPN section youâve got a conventional bipolar transistor that youâd shove electrons in/out the middle of to âfill inâ the middle section such that it conducts by connecting the middle P section to the base. Or, you get a FET by making the insulated capacitor plates on either side and using electric fields to âdragâ electrons around within the structure, causing the extra electrons from the N endcaps to be âsuckedâ deeper and deeper into the P middle section, eventually causing a thin strip of uniform N section where current can flow. More electric field, more âelectron suckageâ, wider strip of conductive material, lower resistance. That uniform section that is formed when electric field is applied and where current subsequently flows is called the âchannelâ. N-channel FET means itâs doped NPN and shrinking the P section gets you an âN channelâ to conduct current through. P-channel FET means itâs doped PNP and shrinking the N section gets you a âP channelâ to conduct current through.
This is all for enhancement mode MOSFETs, which is the most common type. These are devices where the channel is âblockedâ to start with and needs to be âenhancedâ in order to start conducting. Applying gate voltage creates the electric field that enhances the channel so it conducts. The alternative is a depletion mode MOSFET which behaves opposite. The channel initially conducts so it needs to be âdepletedâ to turn off, which is done by applying a gate voltage which creates a magnetic field, etc. etc. There are both N-channel and P-channel version of both enhancement and depletion mode MOSFETs, so it gets real confusing. 90% of the time youâll use an N-channel enhancement mode MOSFET. 9% of the time youâll use a P-channel enhancement mode MOSFET. The remaining 1% of the time youâll use a depletion mode MOSFET and, if youâre anything like me, wonder why the hell you bothered because itâs annoying to get your head around! Enhancement mode MOSFETs are so common these days that you donât even usually need to specify enhancement mode, itâs by far the de-facto standard form. There are also junction FETs which are actually a lot more like the idealised âsemiconducting strip with plates either sideâ I described above but are even less common again in discrete forms. Theyâre super common in ICs and I guarantee there are millions of them within a meter of you right now, but the roles they are best for arenât all that common to hand-design out of individual parts anymore. Mostly ultra-sensitive inputs for amplifier stages, more or less.
The FET name is for Field Effect Transistor, basically describing that relationship. Transistor because itâs a shortening from transresistance, basically a changing resistance device. Field effect because itâs controlled by the electric field created between those capacitor plates, rather than by injecting current directly like a bipolar transistor. So pretty much a capacitor voltage controlling a variable resistance. MOS is metal oxide semiconductor, named for the metal oxide insulator that is used to insulate the gate to create the capacitor such that it can be kept separate from the âpowerâ connections.
Thatâs quite the diversion I just went on, itâs not really âthatâ relevant, itâs just interesting!
So with the P-channel, it all works kinda backwards, if you look at the symbols with the drain at the top and source at the bottom, current flows from source to drain in the P-channel instead of drain to source like in the N-channel, the applied voltage needs to be negative vs the source in the P-channel instead of positive vs the source like the N-channel. Because of the previously mentioned convention behind current flowing top to bottom we usually draw the FETs upside down. The voltage we care about for the gate is the Gate-Source voltage but now the source is at the top of the device, so itâs the voltage at the gate minus the voltage at the top. As you said before, if the gate is pulled down to 5V and the source is connected to 24V, youâve got 5V-24V = -19V as your Vgs. For that same reason youâll see all the graphs in the datasheets are using positive numbers but referencing -Id, -Vds, -Vgs etc. Thatâs just a convention, again, so that theyâre easier to read because they look the same as N-channel devices, just with all the nomenclature reversed.
I mentioned this above but Iâll reiterate it here to directly answer this. There are a couple of different aspects.
The first is that the applied voltage to the gate isnât really about it switching fast or slow, as such. As above, the drain-source resistance pretty much instantly follows the applied gate voltage. Higher voltage doesnât mean turning on âfasterâ or anything, really, it just means turning on to lower resistance. Thatâs a little bit nit-picky, so sorry about that, but itâs an important distinction later. The next part of it is what youâre doing with that resistance. Weâre talking a lot about âonâ and âoffâ, but in reality all the FET is doing is being a variable resistor. In this case weâre talking about the voltage at the terminals being high or low, meaning that some other logic device downstream can look at it and say âthis is logic highâ or âthis is logic lowâ.
If we have a lot of capacitance then we need a lot of current to flow through the FET before the voltage starts to change. For that we need to have the FET in a lower resistance state to allow more current to flow and therefore make that voltage change happen faster. If we have less capacitance then we can still have it change voltage fast but without needing to turn the FET on as much, or have it change voltage faster with the FET turned on the same amount, etc.
The second part is that this analysis is what we call a âsteady stateâ analysis. It assumes that everything has settled. I guess the water analogy would be weâre assuming everything is flowing nicely and weâre ignoring situations like taps turning on/off quickly and causing water hammer, things like that.
The gate is a capacitor and the resistance of the FET changes based on how much itâs charged. For argument lets say weâre driving the FETâs gate directly via a resistor, like with the low-side FET thatâs connected directly to the microcontroller. If we look at this in steady state, 3.3V out from the micro means 3.3V on the gate because thereâs nowhere else for any current to go. Letâs say the FET is an imaginary perfect impossible device and its gate has no capacitance. That would mean that regardless of the resistor we use, the gate would look like an open circuit so the voltage on the GPIO pin would be the same as the voltage on the gate. If we instantly change the GPIO pin from 0V to 3.3V, the gate voltage will do the same. In reality that change isnât instant, but itâs way faster than the issues weâre having so we can call it instant, for now.
In reality, thereâs a bit of capacitance on the gate, lets say itâs a 1nF capacitor. Now weâve got an RC filter thatâs created by the resistor between the GPIO pin and the gate. If we assume that the resistor is a 1K resistor then we can use other tools to see what the actual voltage change is at the capacitor (the gate voltage) when a sudden 0V to 3.3V âstepâ is applied. The best tools for this are things like SPICE simulations which can show things in great detail, but an RC filter is simple enough that they can be fully analyzed mathematically and there are websites that will show you key features.
The short answer, though, is that it takes time for the voltage to change because the capacitor needs current to flow into it to âcharge upâ, and the resistor limits how much current can flow.
Throwing that circuit into LTspice (the most common freely available circuit simulation tool), I create a voltage source that changes from 0V to 3.3V in 50ns which should mimic the GPIO on the ESP32. That then feeds into a 1K resistor and a 1nF capacitor. I can âprobeâ the voltages at both the GPIO pin and the capacitor and see what happens as a result.
Anyway, thatâs not too bad. That little FET is connected to resistors that are nearly 100K in total so all it needs to do is get to even 1K resistance and itâs probably on enough for out needs. That happens at a pretty low Vgs so likely itâs only causing a 500ns delay and going from +Vds to 0V quite quickly.
Thatâs actually another thing to consider, there are 2 aspects to timing issues. One is delay, the other is transition time. Delay isnât too bad because we donât care if a PWM signal is offset by a couple of us, as long as it is still the correct PWM and the waveform looks clean. The transition times are what weâre more interested in. Delays do become very important in other situations, though, like communications where it can cause data errors or where it needs to managed to ensure something turns on/off in the right sequence. It can matter where the delay from âonâ to âoffâ is different, too, because if it takes 1us delay before something turns on and 10us delay before it turns off, thatâll change the duty cycle of the PWM, but thatâs a story for another dayâŚ
So we move to the actual problem at hand, which is the next stage, the P-channel stage. This is the same kinda thing as what weâve just looked at, but with a couple of wrinkles⌠Weâre not actually driving the gate from 0V to 24V, weâre just driving it one way by connecting the bottom of that divider to 0V using the N-channel FET and then weâre letting the resistors in the divider âpullâ it back to 24V. Because of this, weâve got 2 competing things weâre trying to design for. One is that we donât want those resistors too low of a value because then when the N-channel FET is on we have a LOT of current from the 24V line. The other is that we donât want the resistors too high because then not much current will flow to charge the gate capacitor.
So chucking THAT circuit into LTspice, it looks like this:
So in that situation, this is what the gate voltage looks like:
Then add to all of this that this is still just the gate voltage, not the actual resistance of the FET and the resulting output, it all gets kinda annoying quickly.
Nothing is ever out of the question, or even necessarily âthatâ difficult, after all we switch 85kHz at 1000V and 250A with no appreciable waveform distortion. Itâs more just that itâs a solid step in complexity beyond what youâve been designing so far. If you think itâs something thatâs valuable to have and important enough to devote a little bit of BOM cost to it should be quite possible.
I think youâre also being led astray somewhat by following other designs that are already a little bit âamateurâ, meaning that in the literal sense, not a pejorative one. The assumption being that hopefully they work fine and donât have issues but you never know, especially because I still suspect that most people when something goes wrong tend to assume they did something wrong themselves rather than it being just a random issue with a design being on the edge of operative spec etc.
If youâre dead set on wanting 24V PWM there are some options. One would be to do our own half-bridge drive, where itâs both top and bottom switched, or to use something as a high current buffer like a gate driver IC etc. There are ways, it just might take me a week to get enough time to look into it, if youâd like some help there.
I canât think of a good reason for either of those.
VMOT should be used for power loads.
5V FET should be used only for slow signals.
PWM outputs should be through a fast buffer/level converter.
Serial out we are already following the FluidNC convention and using up the UARTs.
Well, the issue is that encompasses 3 options which would require 2 methods of adjustment or a 2nd set of headers. Selectable voltage for the high current circuit and then selection of either the high current circuit or low current buffer as an output. I gather that itâs a bit awkward trying to do both.
I think itâs quite plausible to do it in a selectable and also fast-enough manner, just not with the circuit as shown. The follow up question is then whatâs it worth in terms of BOM cost etc.
Got curious and spent a few minutes trolling through Digikey. Itâs âjustâ irritating enough of a problem that there are dozens of approaches but itâs tricky to find the exact one. Auto high-side switches tend to be deliberately slew limited so too slow. Gate driver ICs are more for high current pulses so arenât well specified for DC loads. Most of the half-bridge ICs tend to have some assumptions about what theyâre driving, such as a maximum PWM duty cycle to bootstrap the high side driver, that kinda thing, or are just also too slow. There are some parts thatâll do it but only for Auto voltage ranges, or only for higher than 5V ranges if they extend to 30V and past, other parts that might work it but are $10 each so why bother, etc.
The only one that comes to mind is controlling fan speed. I dug through the fluid wiki as well. There are some 10V PWM spindles but they need thier own module I guess.
Jono thank you, that did help. I am sure the more I read that the more I will understand but I am seeing the time thing a bit more clearly now.
For a case fan, Iâm in the âturn the damned thing on when power comes onâ camp. I leave power to a fan on full time.
For a case fan absolutely. I just donât pay much attention to stuff outside our bubble and obviously I want this to be as universal as possible. The FluidNC wiki lists solenoids, servos, relays, fans, VFD controllers as outputs. Google search pops up DC motor control, 24v LED dimming, and fans. So it seems it is nothing very critcal.
I am now finally okay with no PWM on the 24V side, the 5V PWM is already in the Buffer, 74AHCT125T14-13 | DIODES | Price | In Stock | LCSC Electronics
With that said, I asked for some outside help, let me share the circuit I got back.
If it might need a fan it get it all!!!
On my 3D printers I usually run my fans at 90-95%. They are usually a lot less loud and last a lot longer between replacements. I used to replace fans once a year on the farm. Turning them down, some of them are at nearly 3 years now.
Here is that circuit.
n-channel switching the high side - IRFB7545PBF | Infineon | Price | In Stock | LCSC Electronics
Driver 1EDI40I12AF | Infineon | Price | In Stock | LCSC Electronics
Those two specif ones would be about $1 per output. With the new info Jono shared I will try to see if I can figure it out, n-channel high side. I know I have read about it but I did not think it was a good idea.
That driver is an isolated one so would also need a power supply that can pull the gate up above its source. CUI have some decent ones, but theyâll all be a lot more expensive than the driver and FET.
Itâs a really tricky thing to do. Isolated typically either needs a separate isolated power supply, an expensive integrated one or has other limitations like needs to be at less than 100% duty cycle like gate transformers or bootstrapped drivers. I wouldnât focus too much on the N-channel aspect, thatâs not the issue as much as the voltage translation up to 24V in a way thatâs low impedance.
Low side switching and extra jumpers or switches mean we have something as good or better than the JP1 sharing the same output terminals if it can all fit.
Let me get to work combining the two and see how it goes.
We put in a hell of a fight to do high side switching, but jut not worth it. 24V PWM is not needed bit feels like going backwards not having it. Might not be able to get 4 switchable outputs but I would be happy with at least two.
I just canât help but keep poking around.
SKR Pro, is 12-24V, lowside switched.
EE is pretty wild.
If you revert to low side switching, do you want to consider some kind of protection for shorting the high side? Fuse or polyfuse or ??
I donât think so. I have not seen any boards with them other than ramps polyfuses.
If I can figure out a good connector, I donât see an easy way to short anything. Thinking 8 sockets, and only 4 plugs.
I hate this. We lose the easy-to-use output terminal and are back to screw terminals, with plugs that are ordered separate.
Back to me order multiple things from multiple suppliers. This makes international direct harder again. The whole point was simple easy to scale. Try to bring the cost down
Almost impossible to do with such small FETs. They usually die long before the fuse and any replaceable options are likely worse.
Just letting the FET go pop isnât a bad protection method, albeit a little bit âagriculturalââŚ
Series resistors needed on the outputs of that buffer, just 100R or so. Personally Iâd have something like a 1nF cap as well. That will cut some of the high frequencies and avoid cross coupling to other signals.
I would also add 100nF caps near the switched outputs.
Also, donât trust anything on the SKR pro. The way they did their end stop inputs is like first year EE grad level mistake. Just appalling. Be cautious, thereâs a lot of garbage out there that kinda mostly works but weâve all seen how that end stop situation played out.
