How do you know it popped? That zit on top?
Multiple zits. Itās toast.
What should I do?
Please send it in. If you need details.
Sure. Where should I send it? Do I need a reference number?
I need your order number since your name and email do not match any orders I have. Or you can PM me your email that you used for the order, do not post your email publicly.
Iāll be interested to see what you find with reworking that. That LDO should have on-board temp/current limiting so it shouldnāt be possible to kill it with thermal/load issues. There are diodes on the input so it shouldnāt be possible to reverse the polarity on it without also killing those. Applying >15V on the 5V could do it. Applying a higher voltage on the 3.3V output could do it. Any amount of back-feeding from the 3.3V to the 5V could do it as well.
So forced motion on the steppers causing Vmot to rise could cause the internal stepper driver LDO to liven and Vcc_io to start sourcing current. That would happen for a bit before the 5V SMPS came out of undervoltage lockout so that seems the most plausible option, to me.
Ryan: Perhaps plan for a ~2A schottky across the LDO in the next revision. Cathode to +5V, anode to +3.3V. That may prevent that issue. Could also tack one onto an existing test board and try to kill it.
That is interesting. I didnāt think we actually had to worry about steppers feeding back anymore. Shoot, I am not sure why I thought that but protecting this could be an option.
This is the first we have seen of this, I am very interested to see what else is going on with it.
Yeah, I wouldnāt worry too much about adding that protection at the moment. Iād add it in future just for the sake of it, but I wouldnāt do a revision now to add it. I would, however, do a bit of testing on it just to checkā¦
I would hook scope probes up to 3.3V, 5V and Vmot lines, set the timebase to ~10s per division and then start moving the gantry around. Slowly at first then speeding up.
If Iām correct, Iād expect to see Vmot, 3.3V and 5V all rise together, which would mean that the internal TMC LDO is turning on and feeding the 3.3V rail and then back-feeding the 5V through the external LDO.
It could even be that the 3.3V rail will rise well above 5V, which could also damage that external LDO.
Ryan bookmark edit - jp3feedbacktest
Put on a new 3.3V reg and it popped as soon as I hit it with the 24v input.
On USB only the esp did not power up.
Under the microscope everything seems to be fine. I need to follow the 24v rail round to see what could possibly be going on.
If USB power doesnāt work and the new 3.3 died immediately, iād suspect a problem on the 3.3V rail, no?
Yeah, you are right.
Correct assessment
Pull the regulator again and measure the 3v3 power rail resistance. Youāre chasing a short or component with a failure that looks like a short.
then, power up again from VMot with the regulator removed. What is thin voltage coming in the the pads where the regulator goes?
Not enough resistance on anything on the 3.3v to see a difference. With the reg off the 24v side seems perfect, nothing leaking to the 3.3v side either.
There really is not much on the 3.3v side, maybe an esp32 gone bad?
You know what the USB chip does not register when I plug it in. Even on the other bad board, the USB still connects.
Not sure I can pull this chip off or not, just think it would be valuable to know.
Itās a bad board. Do you have a bench top power supply?
Might inject a current limited 3.3V and see what gets hot.
Iād pull that USB chip and see what you see.
If this is a back emf popped board, lots of stuff could be fried.
Oh, YES, now that is fun. I will do that for sure.