Looked like ESP32 Node MCU was pluggable to me, nice and easy to replace/upgrade, plus enables sourcing options for build. Only saw 1 header row per side instead of the doubled headers on original board. ESP32 modules come in diff widths. So, using single headers will limit Module options, and pin breakout options.
Hey @vicious1, intentionally using single row headers for ESP32 module?
Youâre speaking my language there, 100%. Testing and iterating is super important because itâs how you ensure that any mistakes are caught and corrected. Peer review is how you avoid a ton of those mistakes in the first place! A 1 hour review can easily save 5-6 hours in the lab and a week or 2 on a gantt chart.
It does have to be âgoodâ peer review, though. Iâve sat through a few too many where people are just there to tick the box and wonât ask questions etc.
Speaking to the specific images of the design above, definitely use more copper. Copper is free (or at least, youâve already paid for it) and most places donât charge for vias anymore so itâs worth leaning on heavily. In fact, for power stuff Iâll often route it as a poured polygon where the shape for it is a little âweirdâ. Itâs also easy to get super fixated on minimized resistance but it often matters less than minimizing inductance. Resistance is important for reliable voltages at spread nodes around the board and avoiding heating the board too much. Inductance is what actually breaks designs. In general, Iâd prefer cleaner routing over thicker traces almost every time.
Is that image a 2 layer design currently? With a 2 layer design itâs critically important to consider the return path of each of your signals. Long parallel traces like that are usually fine. Unless theyâre super sensitive or have dramatically high speed edges, the amount of cross-talk youâll get isnât too bad. Where the issues come in are from breaks in the return path that get shared between the signals. A slot in the ground plane under the traces means that any return currents will need to deviate from flowing directly under the trace which adds a lot of inductance (leading to ringing, slow edges, higher emissions, lower immunity etc.) but worse it adds a lot of coupled inductance between both traces (dramatically higher cross-talk, etc.).
Iâm a software engineer by trade. My reviews are usually offline, with tools that let you look through the changes line by line and have asynchronous questions and answers.
But there are still people who just check the box. Obviously, that doesnât help improve quality.
There is also a problem at the other end of the spectrum. At least in software PRs, the goal is improvement, not perfection. Some reviews never end because the code is never perfect and the goal posts move. We can maybe accept less quality because an update is easier than in hardware.
That sounds like a neat approach, I guess thatâs one of the advantages of so much of the software design process being fundamentally text and human readable. Itâs a bit easier to layer collaboration tools on top of it.
Managing that conflict between âgood enoughâ and âperfectâ is definitely a thing in hardware, too. Itâs hard because if thereâs an issue then it should be raised and noted, but it can quickly feel like nit-picking if there isnât a clear path forward to a solution. The way I always approach it is that Iâm clear that I will bring up every potential issue that I see and, where possible, suggest clear and actionable fixes but ultimately itâs up to the primary designer of the board to take responsibility for whatever feedback is taken on board and how changes are made.
I had one project where the designer and I had a clear disagreement on a specific issue where it was somewhat of a âdamned if you do, damned if you donâtâ kind of thing. The concession was that my objection was noted and if the issue occurred then he owed me a beer. He was a good sport about it and brought me a beer from a local brewery next time I was in the country anyway.
I think for hardware stuff it helps to have an asynchronous portion ahead of time to familiarize yourself and prepare a list of questions, because so little of the design is inherently âself documentingâ. This is where having notes on a schematic about expected power loss in passives, corner frequencies and step responses of filters, expected frequencies/bandwidths of input signals, required rise-time specs etc. all helps to make it easier to double-check. Then an âin-personâ review where the key requirements of the design get explained and looked at alongside the schematics and layouts. Itâs a lot easier, to me at least, to discuss design intent and consider how competing objectives were weighed against one another in a slightly more âhands onâ fashion like that.
Heck yeah!
Pluggable. There seems to be a new version of the esp coming out the s3, same footprint, they are already working on with in Fluidnc. Not sore of the benefits other than a few pins have some more options.
Yeah I donât think the other size is common anymore.
Yes, currently 2 layer. I donât think anything here would be considered high speed though. I could be wrong.
Well I am excited to learn 4 layer stuff. I will look it up see what I should be doing as the basics and see how it goes. It will still need to be at least 6 drivers long, but it should be able to get skinnier. This sounds fun.
Iâll move back over to the other thread to provide more detail. Custom Bart Dring 6 pack controller
One thing you might find interesting is that even if there arenât any high-speed traces, a lot of the same techniques that improve signal integrity on high-speed traces also improve resistance to external noise sources. After all, inductance is just a measure of how much magnetic flux is created in response to a unit of current. More magnetic flux created per unit of current also means more current induced due to external magnetic fields, etc.
As for the 4 layer board, itâs super easy once youâve kinda done it once. The standard method is to treat the outer layers as purely routing layers and the inner layers as power distribution/signal return layers. Obviously you can only place components on the outer layers (unless stuff gets real crazy), but also it pays to bear in mind that rework and blue-wiring can only really be done on the outer layers, so prioritizing keeping the âfinnickyâ parts of the circuit on the surface helps.
One inner layer as a ground plane means that regardless of what you do with the routing layers, thereâs always a low-inductance return path directly underneath your signal trace. Having a single big ground plane means that you can usually disregard things like where high-current signals are flowing because usually the resistance of the ground plane is so much lower than the resistance of the signal trace that you can safely assume there is no voltage rise across any 2 points of the plane.
The other inner layer as a power plane means that youâve always got power available wherever you need it without specifically routing for it. It also means that youâve got 2 big expanses of copper adjacent to one another that form a capacitor. The value of that capacitor isnât high, but the frequency performance is unbeatable. In a similar fashion to how you would have electrolytic capacitors for DC to 100kHz, then class-2 ceramic capacitors to handle up to 10-100MHz and then class-1 ceramic capacitors to handle up to >1GHz, the PCB capacitance can easily go well beyond 10GHz because the limiting factor for a lumped passive like a capacitor is always the lead inductance, whereas with the power planes that inductance is minimized.
My usual approach with the power plane on a 4 layer board is to try split it up so that itâs handling all of the power nets. If you highlight all the members of each power net, itâs usually obvious what the shapes of those sections of plane should be. For instance, in a design with a microcontroller that has 3.3V and 5V power connections, 5V logic and analog feedback then 12/24V power it might end up with a 3.3V square plane directly under the microcontroller, a 24V âhaloâ around the edge of the board or down one side and then the rest of the board flooded in 5V.
Another neat trick is that as long as there is adequate high frequency capacitance at all the ICs etc. then either plane can be used as an AC return path. A signal can be decomposed into all of its contents, so a 0-5V 100kHz signal with a 1us rise time would have everything from the DC component up to ~10MHz. The DC path can (and often will) be entirely different to the 10MHz path. The DC will generally spread out based on resistance while the 10MHz will entirely be controlled by the inductance. A brief 10MHz âchirpâ on each edge transition and can return by either the ground plane:
Out of GPIO at IC 1, along the signal trace, into the input pin of IC2, out the ground pin of IC2, into the ground plane, along the ground plane under the signal trace, into the ground connection of a de-coupling cap near IC1, along the positive supply trace from that de-coupling cap into the power connection of IC1.
Or via the power plane:
Out of GPIO at IC 1, along the signal trace, into the input pin of IC2, out the ground pin of IC2, into the ground connection of the de-coupling cap near IC2, out of the positive supply trace from the de-coupling cap and into the power plane, along the power plane under the signal trace, into the power supply trace of IC1.
Or, realistically, some blend of both.
Some other random thoughts:
Try to keep the connections to the planes equal for both pins of passives, etc. Having one side pinned with a lot of vias and the other side only connected to a thin trace can cause the solder to flow quicker on one side than the other and âtombstoneâ the components.
Thereâs a balance between not enough copper connection (high resistance, voltage drop under load) and too much copper (too much thermal mass, poor joints because solder doesnât flow well). When in doubt, try to take it back to âreal worldâ numbers, like using Saturn PCB Design or similar to estimate the resistance of a via or trace and ask yourself whether 100nV of voltage drop is actually needed etc.
For any important signals, it can help to actually draw out the expected loop path. For signals that have critical EMI/EMC ramifications Iâll often do a drawing of where each current loop is in a switch mode power supply and provide that for review along with the design. Literally a screenshot with coloured pen markings showing where the current should be flowing in each state of the power switches etc.
Thank you for the tips. I didnât understand or follow all of it but I what I did get I understood. I can look up some of the other stuff. If all the components are on one side, that is obviously a signal plane, what is best next, ground or power?
The best that can be had is about 15mm in one direction on this current board, and that leaves no enough room for labels. So I actually think this board is pretty good as is. I might try to knock off 5mm but I will save the 4 layer for after we get some in the hands of you guys to test them out. That gives me a lot of time to learn and do several revisions.
Apologies if any of it went too in-depth, itâs tough to know how to aim advice like that sometimes. I love talking about this kinda stuff so please feel free to ask any questions about any of it, regardless of whether itâs high level concept or low level detail stuff.
For figuring out what layer is what, there are a couple of approaches and it usually just depends on packaging or how the design makes sense when looking at it. Typically, I would define any layer that has through-hole components stuffed from that side as the top layer. The bottom layer would be the only layer that gets wave soldered or selective soldered. Then from there the SMT components can go on either side. Top side is typical in my designs because Iâm not usually super constrained by size and that makes it easier to probe/debug with a board the âcorrectâ way up. Bottom side or both sides for SMT components can work well if there are a lot of large through-hole components on the top because they can be placed under the through-hold components. Bottom side SMT components usually mean you canât wave-solder the board as through-hole soldering happens after SMT reflow soldering. It can be done with a selective solder process, but that needs care to make sure that all the SMT components are spaced away from through-hole pads. I usually add lines on a mechanical layer around all the through-hole pads to make sure I donât accidentally put components there. These days thatâs often just connectors and a few big electrolytic caps, etc. which makes that easier.
It doesnât matter anywhere near as much what the order of the internal planes are, for the same reason I mentioned above as the return paths being able to use either. Typically, the ground plane is the better return path as itâs more likely to be unbroken, so I would put that closest to wherever the critical signals are. In a SMT heavy design, thatâs likely to be layer 2 (the 2nd from the top when looking âdownâ at the board). Power would then be layer 3, routing 2 would be the bottom. I used to put a number or bit of text on each layer so show which was which, but Iâve found that things are much more standardized now. You can change the order of the planes if you want, but itâs difficult to know for sure which option is better.
So easiest approach is SMT and PTH components all on the top, L2 as GND, L3 as power, routing/signal layer on both top/bottom with the longest/cleanest traces on the bottom layer and the messier connection or point-to-point traces on the top.
Hopefully that makes sense?
That sounds like a decent approach, thereâs definitely a down-side to cramming it down to being too small and losing things like labels etc.
If youâre sticking with the 2 layer board then Iâd definitely encourage you to go through the exercise of drawing the forward and return path for each signal. Itâs an exceptionally helpful process for figuring out where there might be issues with ground plane impedance and cross-talk, etc. Iâd recommend aiming for traces to be over the ground plane as much of the time as possible and anywhere that the plane is interrupted by a trace going across it, make the interruption as ânarrowâ in all directions as possible.
That looks like a good illustration of what Iâm trying to say.
No need to apologize. I am enjoying all this learningâŚand putting together a puzzle and Tetris at the same time. I just wanted to make sure I wasnât acting like I understood that all.
There will be questions, lots of questions.
Yeah, we did run into that slightly. He was concerned about the ground path and did just that, drew a line to show me. It really is crazy how this stuff works.
I will be trying my hand at designing the whole thing from scratch here shortly I am sure. I just found Arc traces instead of 45âsâŚooooohhhhh fancy!
Once this passes the tests, I am interested to see what you guys do with the layout, there is so many options.
Hahaha, all good. If you look through some old hand-taped or hand-drawn designs, there are some crazy ones that are all curves and look awesome. Iâve wanted to do an âall-arcsâ board layout for a while, just for fun. Ultimately it doesnât make any difference until youâre well, well into the GHz range, but it definitely looks cool.
The return path stuff is something thatâs a big revelation for a lot of designers. There are a few key realizations that often feel obvious in retrospect, but can be real light-bulb moments. For me, one of the things that has been the most important has been to consider all signals as a decomposition of different frequencies (fourier series, if you ever studied that?) and that each frequency band can be considered somewhat separately. Then layer on top of that all the parasitic components that are around: traces have inductance, resistance and capacitance, pins often have resistance and capacitance, all passives have somewhat complex impedances which can also change with frequency, no component is ever truly what it says on its label, all specifications have tolerances with their own distributions and error bars etc.
Most of this can be ignored if you know and follow âbest practiceâ type guidelines, but itâs always useful to know how that stuff works because if you donât just âknowâ how to do something, you can normally use those principals to figure out the things that might be important and then go from there to try and figure out some âreal worldâ numbers for each thing.
Yeah, for sure. Looking forward to going over it a bit.
Watched these a while back when curious about grounding/signaling return path practices. Curious if you/others would recommend these, and/or something else?
Edit: fwiw - I stumbled onto Rick Hartley and Altium content thanks to Philâs Lab channel which has more bite sized content :
I havenât kept up with the Altium training stuff, but the webinars Iâve watched and events Iâve attended personally in the past have pretty much been top quality.
If anything, sometimes I think educational content like this can err too much on the side of showing best practice and what you âshouldâ do, without necessarily explaining the âwhyâ or âwhat happens if you donâtâ side of things. Iâm a firm believer that knowing the rules is good, but understanding them is better, because if you understand them then you can break them 
Just watched the first 20 minutes of the Rick Hartley presentation above and Iâm already inclined to say that itâs pretty damn good. Immediately starting out into pointing out that the energy is in the electric/magnetic fields and that the copper features are there to manage those fields is exactly what I was starting to get into above.
Iâm interested to see what happens if anything on the 4 layer front. When I got familiar with pcb design it was with eagle, and back when anything more than 2layer was a lot more expensive to have made. These days we have diptrace for free 4 layer designs, and very cheap pcb manufacturing to go with it. What software are you using to design this Ryan?
EasyEDA, free and hooked up to the database for easy ordering and a big catalog. I was also told it transfers over to a few board houses.
It depends a lot on the quantity. A 4 layer design is still roughly 1.5x to 2x the cost of a dual layer design, but the cost of PCBs has come down so much that it needs to be considered in terms of the percentage of overall design cost.
In 1k-10k quantities, the cost for a 100x50 (4"x2") board is around ~USD0.40 for double layer, USD0.70 for 4 layer.